The present invention relates to a signal generation circuit of a semiconductor testing apparatus, and particularly to a signal generation circuit provided with a skew correction function.
Conventionally, a semiconductor testing apparatus to test a semiconductor memory, has a signal generation circuit to generate a plurality of channel signals, and the signal generation circuit is composed of a plurality of format channels to generate signals according to a program in which testing procedure is written. The format channel is provided for each signal channel, and by composing a plurality of timing edges, generates a set-edge and reset-edge signals which regulate signals to be applied onto an object to be tested.
Herein, in the testing apparatus, because the transmission path of each timing edge signal is not necessarily the same, there is a skew between respective signals before composition, and signals are not applied on the testing object at the designated timing by the program. Therefore, in the signal generation circuit of the semiconductor testing apparatus, a skew correction circuit to correct the skew between respective signals before composition, is provided.
In FIG. 5, the structure of the conventional signal generation circuit of the semiconductor testing apparatus is shown. In the drawing, numerals 1 and 2 are format channels, numeral 61 and 62 are logical add circuits to conduct the logical add of each of outputs of two format channels 1 and 2. Herein, the format channel 1 is structured by: clock selection circuits 11 to 13 which receive a plurality of timing edge signals from a timing generation section, not shown, and select one of them; a formatter circuit 21 to separate the output edge of the clock selection circuits 11 to 13 into a set-edge or a reset-edge; skew correction circuits 31 to 34 to correct the timing of the set-edge or reset-edge outputted from the formatter circuit 21; and logical add circuits 41 and 42 to conduct the logical add of respective set-edge and reset-edge whose skews are corrected.
Another format channel 2 is structured in the same manner as the format channel 1, and structured by: clock selection circuits 14 to 16 corresponding to clock selection circuits 11 to 13; a formatter circuit 22 corresponding to the formatter circuit 21; skew correction circuits 35 to 38 corresponding to skew correction circuits 31 to 34; and logical add circuits 43 and 44 corresponding to logical add circuits 41 and 42.
Next, operations of the signal generation circuit will be described. Initially, concerning a case of a normal mode in which separate signal s are generate d by each format channel, the format channel 1 will be described as an example.
The clock selection circuits 11 to 13 select one of timing edges described in a program for the tested device measurement from a plurality of timing edges generated from the timing generation section, not shown, and respectively output and supply it to the formatter circuit 21.
The formatter circuit 21 separates the edge signal inputted from each clock selection circuit into the set-edge and the reset-edge so that the waveform designated by the program can be applied onto the device. The set-edge and the reset-edge determine, for example, a rise timing and a fall timing of an address signal, and regulate the timing of each edge of the signal applied onto the tested device. When the formatter circuit 21 separates the edge signal from each clock selection circuit as the set-edge, the formatter circuit 21 outputs it to the logical add circuit 41, and when the formatter circuit 21 separates the edge signal from each clock selection circuit as the reset-edge, the formatter circuit 21 outputs it to the logical add circuit 42.
The skew correction circuits 31 to 34 correct the skew between signals inputted into logical add circuits 41 and 42. Concretely, the skew correction circuits 31 and 32 correct the set-edges respectively outputted from the formatter circuit 21 to the logical add circuit 41 according to the timing edge from the clock selection circuits 11 and 13, so that the same timing as that of the set-edge outputted from the formatter circuit 21 to the logical add circuit 41 can be obtained, according to the timing edge from the clock selection circuit 12. According to this, each set-edge is inputted into the logical add circuit 41 at the same timing.
Further, in the same manner, the skew correction circuits 33 and 34 correct the reset-edge outputted from the formatter circuit 21 to the logical add circuit 42 according to the timing edge from the clock selection circuits 11 and 13, so that the same timing can be obtained as the reset-edge outputted to the logical add circuit 42, according to the timing edge from the clock selection circuit 12. According to this, each set-edge is inputted into the logical add circuit 42 at the same timing.
The logical add circuit 41 conducts the logical add of each of set-edges separated by the formatter circuit 21, and composes them. That is, the logical add circuit 41 outputs a signal in which each set-edge outputted from the formatter circuit 21 is arranged. In the same manner, the logical add circuit 42 conducts the logical add of each of reset-edges separated by the formatter circuit 21, and composes them, and outputs a signal in which each set-edge is arranged.
The format channel 2 is operated in the same manner as the format channel 1, and respectively outputs a signal in which the set-edge is arranged to the channel to which the format channel 2 is allocated, and a signal in which the reset-edge is arranged, from the logical add circuits 43 and 44.
Incidentally, in this operation mode, signals of each format channel are not composed, and because channel signals corresponding to the output signals of each format channel are generated, the logical add circuits 61 and 62 which attribute to the signal composition, do not function. Accordingly, the operation of the logical add circuits 61 and 62 will be described in the next operation of a link mode.
Next, the operation of the link mode by which each format channel is linked and a signal is generated, will be described.
In this operation mode, both of the set-edges of the format channels 1 and 2 are composed by the logical add operation by the logical add circuit 61, and both of the reset-edges are composed by the logical add operation by the logical add circuit 62. That is, in this operation mode, one set signal in which both of each set-edge generated by the format channels 1 and 2 are arranged, is outputted from the logical add circuit 61, and one reset signal in which both of each reset-edge generated by the format channels 1 and 2 are arranged, is outputted from the logical add circuit 62. In this manner, according to this link mode, because apparently 2 time edges can be arranged on one signal, this mode can cope with the high speed device with high operation frequency.
Herein, when the skew between signals outputted from each of format channels is corrected in this link mode, for example, the output from the format channel 2 is corrected so that this output is outputted from the logical add circuit 61 at the same timing as the output of the format channel 1 by using the skew correction circuits 35 to 38.
Incidentally, according to the above-described conventional signal generation circuit, because the skew correction circuits 35 to 38 to correct the output of the format channel 2 at the time of the link mode, are also the circuits used at the time of the normal mode, there is a problem that, every time when the link mode and the normal mode are switched, it is necessary to send again the correction data appropriate for each mode to the skew correction circuits 35 to 38.
Further, in the link mode, because any one of skew correction circuits of 2 format channels is used and the skew correction for only one circuit can be conducted, there is a problem that the number of devices to be measured, which is operated at high speed, is reduced by half.
The invention is attained in view of the foregoing circumstances, and an object of the invention is to provide a signal generation circuit of a semiconductor testing apparatus by which the data transfer amount to the skew correction circuit can be reduced when 2 operation modes of the link mode and the normal mode are switched, and without reducing the number of effective channels and the number of devices to be measured, each of format channels can be used simultaneously, thereby, the measuring time of the integrated circuit to be tested can be reduced.
In order to attain the above object, this invention provides a circuit to conduct again the skew correction of the output of the format channel.
That is, this invention comprises: a plurality of signal generation sections (for example, a component corresponding to formatter circuits 1 and 23, which will be described later) to generate and output signals according to the waveform information designated by a program; a plurality of skew correction sections (for example, components corresponding to skew correction circuits 51 to 54, which will be described later) which are provided corresponding to the plurality of signal generation sections, and in which a signal outputted from the corresponding signal generation section is used as the reference, and by which the skews of the signals outputted from the other signal generation sections are corrected; and a plurality of signal composition sections (for example, components corresponding to the logical add circuits 61 to 64, which will be described later) which are provided corresponding to the plurality of skew correction sections, and by which the signal from the corresponding skew correction section and the signal from the signal generation section to which this skew correction section corresponds, are composed.
According to this invention, each skew correction section uses a signal outputted from the corresponding signal generation section as the reference, and corrects the skews of the signals outputted from the other signal generation sections so that their timing matches with the signal as the reference. According to this, the skew between signals from the signal generation section and the skew correction section, which correspond to each other, is eliminated, and these signals are composed to one signal by the signal composition section.
Each of the plurality of signal generation sections comprises: for example, a plurality of selection circuits (for example, components corresponding to clock selection circuits 11 to 13, 14 to 16, which will be described later) which respectively select one from a plurality of timing edges prepared previously according to the waveform information; a formatter circuit (for example, components corresponding to formatter circuits 1 and 2, which will be described later) which separates each timing edge selected by the plurality of selection circuits, into the set-edge and the reset-edge and output it, according to the waveform information; the first skew correction circuits (for example, components corresponding to skew correction circuits 31, 32, 35 and 36, which will be described later) which correct the skews between each of set edges separated by the formatter circuit; the second skew correction circuits (for example, components corresponding to skew correction circuits 33, 34, 37 and 38, which will be described later) which correct the skews between each of reset edges separated by the formatter circuit; the first logical add circuit (for example, components corresponding to logical add circuits 41 and 43, which will be described later) which conducts the logical add of the set-edges whose skew are corrected by the first skew correction circuits; and the second logical add circuit (for example, components corresponding to logical add circuits 42 and 44, which will be described later) which conducts the logical add of the reset-edges whose skew are corrected by the second skew correction circuits.
According to this structure, the timing edge selected by each selection circuit is inputted into the formatter circuit. The formatter circuit separates each timing edge inputted from each selection circuit respectively into the set-edge and the reset-edge. The first skew correction circuit corrects the skew between each of set-edges generated from each timing edge, and the second skew correction circuit corrects the skew between each of reset-edges generated from each timing edge. The first logical add circuit conducts the logical add of the set-edges whose skews are corrected, and composes the set-edges, and the second logical add circuit conducts the logical add of the reset-edges whose skews are corrected, and composes the reset-edges. According to this, the signal whose skew is corrected can be generated according to the waveform information designated by the program, and the set-edge and the reset-edge whose skews are respectively corrected, and each of which is respectively composed, can be obtained.
Herein, the plurality of signal composition sections is composed of, for example, logical add circuits (for example, components corresponding to logical add circuits 61 to 64, which will be described later), and the plurality of skew correction sections are composed of, for example, delay circuits. Skew correction sections (for example, components corresponding to numerals 71A, 71B to 74A and 74B, which will be described later) to correct the skew between each of signals respectively outputted from the plurality of signal composition sections, may be further provided. According to this, the skew of the signal outputted from each signal composition section can be corrected, thereby, the skew between these signals can be eliminated.
Further, this invention is a signal generation circuit of a semiconductor testing apparatus which has a plurality of selection circuits (for example, components corresponding to clock selection circuits 11 to 13, 14 to 16, which will be described later) to sect one from a plurality of timing edges, and in which outputs of the selection circuits are connected to a formatter circuit (for example, a component corresponding to formatter circuits 1 and 2, which will be described later), and outputs from the formatter circuit are connected to logical add circuits (for example, components corresponding to skew correction circuits 31 to 34, 35 to 38, which will be described later), and the output of the logical add circuit is connected to a composition circuit (for example, a component corresponding to logical add circuits 61 to 64, which will be described later) by which the output of the logical add circuit and the other same output are composed, the signal generation circuit of a semiconductor testing apparatus is characterized in that: a correction circuit (for example, a component corresponding to skew correction circuits 51 to 54, which will be described later) to correct the skew of the signal inputted from the logical add circuit to the composition circuit is provided.
According to this structure, because the correction circuit corrects the skew of the signal outputted from the logical add circuit, the timing of the signals inputted into the composition circuit matches with each other, and signals are composed under the condition that the skew is eliminated.